FIG. 1 shows a CMOS semiconductordevice 12 which includes a plurality of transistor structures, an example of which is indicated generally at 14. Each transistor structure 14 includes a gate 16 which is deposited on an insulation layer 18. The gate 16 and the insulation layer 18 form a gate stack 20 overlying a silicon region 22. The gate stack 20 is formed in a dielectric layer 24. Each silicon region 20 is doped as appropriate to form the desired array of p-type and n-type channel transistors.
The insulation layer 18 may be formed of a variety of insulative materials including silicon dioxide and HfSiOx, depending upon the particular application. Such insulative layers may be deposited on a wafer using various tools including chemical vapor deposition (CVD) chambers which deposit an insulative film by introducing one or more deposition gasses into a chamber. Insulative films may be deposited using other tools such as physical vapor deposition (PVD) chambers which sputter a target to dislodge material from the target and deposit it on the wafer. The sputtered target material may be deposited in a pure form from the target or may react with various working gasses such as oxygen, for example, introduced into the chamber to deposit a reaction compound on the wafer.
To provide certain properties to the insulation film, the deposited insulation layer may undergo various treatments. For example, the insulation layer may be annealed, that is, treated with heat. Other treatments include nitridation which introduces nitrogen into the insulation layer. One such tool for nitridation is the decoupled plasma nitridation (DPN) chamber which utilizes a plasma for the nitridation process.
The gate 16 is typically formed of a conductive semiconductor material such as polysilicon. Alternatively, the gate 16 may be formed of a conductive metal including various metal alloys such as tantalum nitride and titanium nitride. A variety of tools may be used to deposit the gate 16. CVD and PVD chambers may be used to deposit a conductive film to form a gate. The gate stack 20 may have additional layers deposited on the gate 16 and may undergo various treatments including anneal treatments.
FIG. 2 shows an example of a known platform 50 having a plurality of tools including processing chambers 52 coupled to ports of a mainframe 54. A front opening unified pod (FOUP) 56 carrying a stack of wafers may be coupled to a front end 58 which includes a robot 60 which transfers wafers, typically one at a time, from a FOUP 56 to a load lock chamber 62 of the mainframe 54. The interiors of the mainframe 54 and the processing chambers 52 are typically maintained at a very low pressure, often referred to as a vacuum pressure. After the load lock chamber 62 is pumped down to a low vacuum pressure, a mainframe robot 64 transfers the wafer to one or more of the processing chambers 52 to be processed. Processing may include deposition of a material. Other processing may include various treatments including orienting, cleaning, etching, annealing and chemical processing including nitridation, for example.
The mainframe 54 may have a plurality of mainframe robots 64 and a plurality of transfer chambers 66 through which wafers may be transferred from one mainframe robot 64 to another. Wafer processing may also occur in the transfer chambers 66. Such processing may include etching, cleaning, and wafer cooling, for example. Because the entire interior of the mainframe 54 may be maintained at a low vacuum pressure, a wafer may be transferred from chamber to chamber for processing without exposing the wafer to the pressure and contaminants of ambient air until processing is complete and the wafer is returned to a loadlock chamber 62.
Fabrication of a semiconductor device such as a gate stack may utilize a number of different processing chambers which may be coupled to a number of different platforms with robots to transfer the wafers being processed to the different chambers of each platform. Other processing chambers and processing devices such as anneal ovens may be stand alone devices. One known platform capable of fabricating an entire poly-silicon gate stack without exposing the wafer to the pressure and contaminants of ambient air until the gate stack is complete is the Applied Centura Ultima HDP-CVD platform by Applied Materials, Inc. The Applied Centura Ultima HDP-CVD combines base oxide growth in a CVD chamber, with decoupled plasma nitridation in an PNA chamber, both of which are secured to a single platform. A post nitridation anneal is performed in a PNA chamber also attached to the single platform. A CVD chamber which is also coupled to the single platform, deposits polysilicon on the stack to form the gate electrode of the stack.